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data sheet ics840272agi revision a july 26, 2010 1 ?2010 integrated device technology, inc. synchronous ethernet frequency translator ICS840272I general description the ICS840272I is a pll-based frequency translator intended for use in synchronous ethernet applications. this high performance device is optimized to generate 25mhz and 8khz lvcmos clock outputs. the ICS840272I accepts the following differential or single-ended input signals: 161 .1328125mhz (10gbe mode), 156.25mhz (1gbe mode), or 125mhz (recovered clock from 10/100/1000baset ethernet phy). the extended temperature range supports telecommunication and networking end equipment requirements. features ? two single-ended outputs (lvcmos or lvttl levels), output impedance: 17 ? ? single-ended lock detect output (lvcmos or lvttl levels) ? two selectable differential clock inputs ? differential input pair (clkx, nclkx) accepts lvpecl, lvds, lvhstl, sstl, hcsl input levels ? internal resistor bias on nclk pin allows the user to drive clk input with external single-ended (lvcmos/ lvttl) input levels ? selectable input frequencies : 161.1328mhz, 156.25mhz or 125mhz ? output frequency: 25mhz, 8khz ? full 3.3v supply voltage ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd v dda oe sel1 sel0 ref_sel lock_dt v dd v ddo qa qb gnd clk0 nclk0 clk1 nclk1 input control 00 = pll bypass, 25mhz input 01 = 161.1328125mhz (default) 10 = 156.25mhz 11 = 125mhz m qa lock_dt 25mhz 8khz qb clk0 nclk0 pullup/pulldown pulldown clk1 nclk1 ref_sel 0 1 p n pll 0 1 3125 pullup/pulldown pulldown pulldown sel[1:0] pulldown:pullup oe pulldown ICS840272I 16 lead tssop 4.40mm x 5.0mm x 0.925mm package body g package top view pin assignment block diagram
ics840272agi revision a july 26, 2010 2 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1v dd power core supply pin. 2 lock_dt output lock detect. logic high when pll is locked. 3 ref_sel input pulldown selects the input reference clock. when low, selects clk0, nclk0. when high, selects clk1, nclk1. lvcmos/lvttl interface levels. 4 sel0 input pullup selects the input reference frequency a nd the pll bypass mode. see table 3a. lvcmos/lvttl interface levels. 5 sel1 input pulldown selects the input reference frequency a nd the pll bypass mode. see table 3a. lvcmos/lvttl interface levels. 6 oe input pulldown 8khz output enable pin. when low, qb is disabled. when high, qb is enabled. lvcmos/lvttl interface levels. see table 3b. 7v dda power analog supply pin. 8, 13 gnd power power supply ground. 9 nclk1 input pullup/ pulldown inverting differential clock input. internal resistor bias to v dd /2. 10 clk1 input pulldown non-inverting differential clock input. 11 nclk0 input pullup/ pulldown inverting differential clock input. internal resistor bias to v dd /2. 12 clk0 input pulldown non-inverting differential clock input. 14 qb output single-ended clock output. lv cmos/lvttl interface levels. 15 qa output single-ended clock output. lv cmos/lvttl interface levels. 16 v ddo power output supply pin. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance v ddo = 3.465v 17 ?
ics840272agi revision a july 26, 2010 3 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator function tables table 3a. sel[1:0] function table table 3b. oe function table inputs function output (mhz) sel1 sel0 clkx, nclkx (mhz) mode qa 0 0 25 pll bypass 25 0 (default) 1 (default) 161.1328125 pll enabled 25 1 0 156.25 pll enabled 25 1 1 125 pll enabled 25 control input function oe qb output 0 (default) disabled (high impedance) 1enabled
ics840272agi revision a july 26, 2010 4 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo = 3.3v5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = v ddo = 3.3v5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o (lvcmos) -0.5v to v ddo + 0.5v package thermal impedance, ja 81.2 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.11 3.3 v dd v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 57 ma i dda analog supply current 11 ma i ddo output supply current 5ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 3.465v 2 v dd + 0.3 v v il input low voltage v dd = 3.465v -0.3 0.8 v i ih input high current oe, sel1, ref_sel v dd = v in = 3.465v 150 a sel0 v dd = v in = 3.465v 5 a i il input low current oe, sel1, ref_sel v dd = 3.465v, v in = 0v -5 a sel0 v dd = 3.465v, v in = 0v -150 a v oh output high voltage i oh = -12ma 2.6 v v ol output low voltage i ol = 12ma 0.5 v
ics840272agi revision a july 26, 2010 5 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator table 4c. differential dc characteristics, v dd = v ddo = 3.3v5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . ac electrical characteristics table 5. ac characteristics, v dd = v ddo = 3.3v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambi ent operating temperature range, which is established when th e device is mounted in a test socket with maintained trans verse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: refer to phase noise plot. symbol parameter test conditio ns minimum typical maximum units i ih input high current clk[0:1], nclk[0:1] v dd = v in = 3.465v 150 a i il input low current clk[0:1] v dd = 3.465v, v in = 0v -5 a nclk[0:1] v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v symbol parameter test conditions minimum typical maximum units f out output frequency qa 25 mhz qb 8 khz t jit(?) rms phase jitter (random); note 1 qa 25mhz, integration range: 12khz ? 10mhz 1.1 ps t jit(cc) cycle-to-cycle jitter qa 25mhz 37 ps t r / t f output rise/fall time qa 20% to 80% 450 1100 ps qb 20% to 80% 450 1100 ps odc output duty cycle qa 47 53 % qb 47 53 %
ics840272agi revision a july 26, 2010 6 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator typical phase noise at 25mhz noise power dbc hz offset frequency (hz) additive phase jitter @ 25mhz 12khz to 10mhz = 1.1ps (typical)
ics840272agi revision a july 26, 2010 7 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator parameter measureme nt information lvcmos output load ac test circuit output duty cycle/pulse width/period rms phase jitter differential input level output rise/fall time cycle-to-cycle jitter scope qx lvcmos gnd v dd, 1.65v5% -1.65v5% v ddo v dda 1.65v5% t period t pw t period odc = v ddo 2 x 100% t pw qa, qb offset frequency f 1 f 2 phase noise plot rms jitter = area under curve defined by the offset frequency markers noise power nclk[0:1] clk[0:1] v dd gnd v cmr cross points v pp 20% 80% 80% 20% t r t f qa, qb ? ? ? ? v ddorx 2 v ddorx 2 v ddorx 2 t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles qa, qb
ics840272agi revision a july 26, 2010 8 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator applications information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is requir ed. the ICS840272I provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd, v dda and v ddo should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v dda pin. figure 1. power supply filtering recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but ca n be added for additional protection. a 1k ? resistor can be used. clk/nclk inputs for applications not requiring the us e of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. outputs: lvcmos outputs all unused lvcmos output can be le ft floating. there should be no trace attached. v dd v dda 3.3v 10 ? 10f .01f .01f
ics840272agi revision a july 26, 2010 9 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefi ts of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is reco mmended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specific ations are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a diff erential input to accept single-ended levels
ics840272agi revision a july 26, 2010 10 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are exam ples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. clk/nclk input driven by an idt open emitter lvhstl driver figure 3c. clk/nclk input driven by a 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver figure 3f. clk/nclk input driven by a 2.5v sstl driver r1 50 ? r2 50 ? 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 ? r4 125 ? r1 84 ? r2 84 ? 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 ? *r4 33 ? clk nclk 3.3v 3.3v zo = 50 ? zo = 50 ? differential input r1 50 ? r2 50 ? *optional ? r3 and r4 can be 0 ? clk nclk differential input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 ? r2 50 ? r2 50 ? 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 ? zo = 50 ? clk nclk differential input sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 ? r2 120 ? r3 120 ? r4 120 ?
ics840272agi revision a july 26, 2010 11 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator schematic example figure 4 shows an example of ICS840272I applications schematic. in this example, the device is operated at v dd = 3.3v. the input is driven by either a 3.3v lvpecl or lvds driver. two examples of lvcmos terminations are shown in this schematic. the decoupling capacitors should be located as close as possible to the power pin. vdd r2 2.7k ld1 led u1 vdd 1 lock_dt 2 ref_sel 3 sel0 4 sel1 5 oe 6 vdda 7 gnd 8 nclk1 9 clk1 10 nclk0 11 clk0 12 gnd 13 qb 14 qa 15 vddo 16 vdd zo = 50 ohm r7 84 zo = 50 ohm lvpecl r5 84 r4 125 r6 125 vdd to logic input pins optional termination set logic input to '1' logic control input examples set logic input to '0' unused output can be left floating. there should no trace attached to unused output. device characterized with all outputs terminated. to logic input pins vdda vdd zo = 50 ohm r10 100 r9 100 ru2 not install ru1 1k c1 10uf rd2 1k r1 10 r8 35 lvcmos c2 0.01u c3 0.1u lvcmos c4 0.1u zo = 50 ohm rd1 not install vdd vdd vdd vdd zo = 50 ohm zo = 50 ohm lvds r3 100 f igure 4. ICS840272I schematic example
ics840272agi revision a july 26, 2010 12 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator power considerations this section provides information on power dissipation and junction temperature for the ICS840272I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS840272I is the sum of th e core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. power (core) max = v dd_max * (i dd + i dda + i ddo ) = 3.465v *(57ma + 11ma + 5ma) = 252.9mw output impedance r out power dissipation due to loading 50 ? to v dd /2 output current i out = v dd_max / [2 * (50 ? + r out )] = 3.465v / [2 * (50 ? + 17 ? )] = 25.86ma total power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 17 ? * (25.86ma) 2 = 11.4mw per output total power (r out ) = 11.4mw * 2 = 22.8mw total power dissipation total power = power (core) max + total power (r out ) = 252.9mw + 22.8mw = 275.7mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 81.2c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.276w *81.2c/w = 107.4c. th is is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 16 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 81.2c/w 73.9c/w 70.2c/w
ics840272agi revision a july 26, 2010 13 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator reliability information table 7. ja vs. air flow table for a 16 lead tssop transistor count the transistor count for ICS840272I: 3326 package outline and package dimensions package outline - g suffix for 16 lead tssop table 8. package dimensions for 16 lead tssop reference document: jedec publication 95, mo-153 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 81.2c/w 73.9c/w 70.2c/w all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ics840272agi revision a july 26, 2010 14 ?2010 integrated device technology, inc. ICS840272I data sheet synchronous ethernet frequency translator ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 840272agilf 40272ail ?lead-free? 16 lead tssop tube -40 c to 85 c 840272agilft 40272ail ?lead-free? 16 lead tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, su ch as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS840272I data sheet synchronous ethernet frequency translator disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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